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14th chunk of `runtime/doc/indent.txt`
3e599a43f7e82cdc3a78cba8a6345558ff324d22c8ff03da000000010000096f
	Amount of indent to add for case labels.
				(not actually implemented)

b:sh_indent_options["case-statements"]
				Amount of indent to add for case statements.

b:sh_indent_options["case-breaks"]
				Amount of indent to add (or more likely
				remove) for case breaks.

VERILOG							*ft-verilog-indent*

General block statements such as if, for, case, always, initial, function,
specify and begin, etc., are indented.  The module block statements (first
level blocks) are not indented by default.  you can turn on the indent with
setting a variable in the vimrc as follows: >

  let b:verilog_indent_modules = 1

then the module blocks will be indented.  To stop this, remove the variable: >

  :unlet b:verilog_indent_modules

To set the variable only for Verilog file.  The following statements can be
used: >

  au BufReadPost * if exists("b:current_syntax")
  au BufReadPost *   if b:current_syntax == "verilog"
  au BufReadPost *     let b:verilog_indent_modules = 1
  au BufReadPost *   endif
  au BufReadPost * endif

Furthermore, setting the variable b:verilog_indent_width to change the
indenting width (default is 'shiftwidth'): >

  let b:verilog_indent_width = 4
  let b:verilog_indent_width = shiftwidth() * 2

In addition, you can turn the verbose mode for debug issue: >

  let b:verilog_indent_verbose = 1

Make sure to do ":set cmdheight=2" first to allow the display of the message.


VHDL							*ft-vhdl-indent*

Alignment of generic/port mapping statements are performed by default. This
causes the following alignment example: >

  ENTITY sync IS
  PORT (
         clk        : IN  STD_LOGIC;
         reset_n    : IN  STD_LOGIC;
         data_input : IN  STD_LOGIC;
         data_out   : OUT STD_LOGIC
       );
  END ENTITY sync;

To turn this off, add >

  let g:vhdl_indent_genportmap = 0

to the vimrc file, which causes the previous alignment example to change: >

  ENTITY sync IS
  PORT (
    clk        : IN  STD_LOGIC;
    reset_n    : IN  STD_LOGIC;
    data_input : IN  STD_LOGIC;
    data_out   : OUT STD_LOGIC
  );
  END ENTITY sync;


Alignment of right-hand side assignment "<=" statements are performed by
default. This causes the following alignment example: >

  sig_out <= (bus_a(1) AND
             (sig_b OR sig_c)) OR
             (bus_a(0) AND sig_d);

To turn this off, add >

  let g:vhdl_indent_rhsassign = 0

to the vimrc file, which causes the previous alignment
Title: Shell, Verilog, and VHDL Indentation Options
Summary
This section details the configuration of indentation for Shell, Verilog, and VHDL files in Vim. It describes Shell indentation options for case statements and breaks. For Verilog, it explains how to indent module blocks and adjust the indentation width, as well as enable verbose mode for debugging. The VHDL section covers disabling the alignment of generic/port mapping statements and right-hand side assignment statements via variables in the vimrc file.